##### Lecture 6 • 2017/01/25
•  Solution is gate/lock eg and gates around SR flip flop
• To retrieve/send to correct address, use and gates with negations to check for matches.
• JK flip flop – two RS flip flops w/ clock and other gates
• Adds a delay to output (first flip flop changes when clock is 1, other one outputs when clock is 0 → half the outputs as input)
• Half adder only contains A and B inputs
• When doing addition, only least significant digit is half adder, others are full adders as there are carries
• Status register has a few bits for unusual situations → overflow, dividing by 0, sign change
• To build an ALU, we need to know size of inputs and outputs, format, etc
• How would ALU design change when upgrading?
• Subtraction – need to decide how we are doing the operation
• 5 – 3, 5 + (-3), 5 + (3 * -1)
• ALU has its V like shape because there are 2’s complement holders for L & R followed by operation section
• Reminder: 2’s complement – invert all bits and add 1
##### Lecture 7 • 2017/01/30
• Making a calculator: get method to check which digit you need, then turn on appropriate sections accordingly.
• Multiplexers 2a-to-1 mux has 2a inputs x0, … xn-1 & single output z.
• Selector address ‘a’ composed of input signals y0, …, ya-1 selects which xi signal passes through z
• Like a router → multiple data, has to take turns
• Decoder – a-to-2a decoder asserts one and only one of its 2a output lines
• CPU sequencer is decoder
• Input is an index; outputs signal on wire of that index
• Encoder – outputs an a-bit binary number equal to index of single 1 signal among 2a inputs
• Input from one of the wires; outputs index of that wire
• Active output used to tell if x0 is ON as compared to an encoder that is off (otherwise both would be 0000)
• Programmable Combinatorial Parts
• Type 1 – VIA fuses can be “blown” given sufficient current
• Type 2 – VIA anti-fuse “sets” given sufficient current (chemical)
• Drawn as a square, becomes circle
• Blown fuses connects the wires?
• Fuses represented by square
• !!ROM & PROM shorthand
• PROM – programmable read only memory
• PAL – programmable array logic
• Pairs that go down
• PLA – programmable logic array
• Individual lines and or gates forming a hash
• Both arrays programmable
##### Lecture 8 • 2017/02/01
• Encoder/Decoder (see previous lecture)
• Von Neumann Machine – traditional computer model based on Turing’s theoretical ideas
• Model: RAM (input) → Processor (Get instruction) → Execution with control unit → RAM (output)
• Index: MAR – memory address register, MBR – memory buffer register, D0-7 Registers, ALU – arithmetic logic unit, INC – incrementer, PC – program counter, IR – instruction register, CU – control unit, in ram {Mode, AR – address register, DR – data register}
• Sends to DR then to buffer (D0 to D7) – buffer may can contain data or instructions
• Depends on MBR
• Every instruction in binary has two parts; OP code and address (or something else)
• Only OP code goes down to control unit
• IR is basically a “dead end” address will move onto PC, which will increment itself then write into MAR → DR → MBR (overwrites previous content) → next set of instructions
• CPU loop
• AR ← PC
• PC ← PC + 1
• DR ← RAM[AR]
• IR ← DR
• Each line involves one tick (some improvements, like incrementation on same tick)
• Micro Instruction – way to express CPU operation step by step
• [ ] for index like arrays, ( ) for arguments
• IR(OP, params)
• ← indicates move
• BUS – Address, R/W, Data
• 1 bit/wire, bottle neck, duality of operation (modes)
##### Lecture 9 • 2017/02/06
• An instruction can be any size (ie 8, 16, 32 bits) depending on the CPU
• Bite – flip flop
• Byte – 8 flip flops – standard size for RAM
• Word – standard size for CPU
• Address – standard size for bus
• Registers – either Byte, Word, or specialty sizes
• Ports, slots, other important registers – Often "accessible" but not "addressable"
• At least now, sizes should agree with each other
• BUS – conduit for bytes to travel from one location to another (pathway)
• In buses, address and R/W signals are only 1 way; data however is 2 ways, and is sometimes designed as 2 buses
• 1 bit per wire
• Bottle neck; 1 byte of data per movement
• Duality of operation: byte & word modes
• Program (assume 8 bit instruction set)
•  MOV D0, D1 D0 ← D1
•  Add D1, D0, 5 D1 = D0 + 5
•  MOV D0, X D0 gets x from RAM
• Run Program
• OS – double click, load to RAM at free space, PC ← 50
• Program Runs (OS is sleeping; number on top right denotes address)
• MAR50 ← PC50
PC51 ← PC + 151
• AR50 ← MAR56
DR ← RAM[AR]
• MBR ← DR
IR ← MBR
CU ← IR (op code)
• OP code ⇒ code # represents instruction
• Bottom left wires go down to CU
• Args is complicated; sometimes have one, two, three, etc
• For our example, there are always 3 arguments
• Comment: no real difference b/t integers and addresses; just how we use it
• Need code for all instructions?
• Each instruction from set is mode of micro-instructions
• ADD, D1, D0, 5 ⇒ D1 = D0 + 5
• Micro
• L ← D0
• R ← 5
• A ← ALU(L,R)
• D1 ← A
##### Lecture 10 • 2017/02/08
• Midterm – definitions, circuit drawing/interpreting, data conversions & representation, RAM, adder, addressing, bus, IR, IP, classical & pipeline CPU, off the shelf circuits, mathematical problems as seen in assignment
• Pipeline as optimized architecture – clock tick sharing
• CU needs to make sure it goes through all the right loops
• In pipeline, cacheinput → … → cachedata at 2GHz. It is connected to RAM via a slow bus, but to make use of the speed, there are private fast buses going from the RAM to the cache input and data. They operate at 2Ghz + dump, meaning they collect data and send a bunch at once.
• Code/load prediction – dumb vs smart (looking one instruction ahead to see when to dump)
• Fetch portion of CPU