Comp 273 Terms & Concepts

Prof. Joseph Vybihal
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System Board Components
Buslinks everything together
RAMstorage for address and data
Clock(bus & CPU) – regulates data movement
PCI & ISAperipherals (PCI faster)
CPUcontrols math, logic, data, movements & loops
ALULR inputs, A-Out output, status register – math ops
IP, IC, IRkeeps track of instruction
Data Types & Sizes
Nibble4 bits
Byte8 bits
Word16 bits
Long Word32 bits
Quad Word64 bits
Number Representations
Binary (0b), Hexadecimal (0x), Octal (0), Decimal
Two's Complement
Take all bits, flip them, add 1
00111 → 11001
Unique 0 value, auto subtracts
IEEE Format
Single18233228 – 1
Double1115264210 – 1
Quad115111128214 – 1
* Note that mantissa excludes the starting 1, and bias is used to define exponent for 0
Decimal Float to Binary Float
Eg 2.625
  • Convert integer (2 → 10)
  • Repeatedly multiply decimal portion, take unit digit, and repeat (0.625 → 1.25, 0.25 → 0.5, 0.5 → 1.0)
  • Combine (2.625 → 10.101
  • Realign exponent and remove 1 when writing mantissa
Flip Flop
  • D flip flops – direct
  • RS flip flops – reset/set
  • JK flip flops – set/toggle/reset
More Info
  • Encoder – single bit vals 0 to n to a index value
  • Decoder – index val to n branches of single bits
  • Multiplexer – many inputs & index, outputs input at index
  • Demultiplexer – one input & index with many outputs; only outputs input at index; rest 0 or x
CPU Loop Execution (Classical)
  1. MAR ← PC
  2. PC ← PC + 1
  3. AR ← MAR
  4. DR ← RAM[AR]
  5. MBR ← DR
  6. IR ← MBR
  7. CU ← IR(OP-Code)
Pipeline CPU Structure
  • Fetch → Load → ALU → Store
  • Each can execute at own time, allowing for multiple instructions at a time
Micro-Programming Types
  • Flat – one instruction at a time
  • Pipeline – assembly execution of multiple instructions
  • Cores – parallel executions
Hazards & Faults
  • Hazards – dangers to watch for (eg can't control dividing by 0)
  • Fault – error occurred (user divided by 0)
  • Stall – CPU cycle lengthens (eg CPU running faster than code)
Like CPU, but only has things needed to do its specific function (like floating point arithmetic)
Improved Integer Multiplier Circuit
  • Multiplicand data (32 bits)
  • Product data (64 bits) with multiplier value in leftmost 32 bits
  • Calculate multiplicand & leftmost 32 bits of product, then shift product right
  • Repeat until everything is shifted; note that those after the first 32 bits no longer need to be touched (eg only one multiplication is done for the unit digit)
Multiprocessing – Types of Computers
  • Single CPU – one CPU, any type (flat, pipeline, hyper threaded)
  • Multi-CPU – more than one CPU chip, any type; each chip with its data cache, plus shared L2 cache
  • Single Core – optimized single CPU chip; has bridge to connect with system board
  • Multi-Core – single CPU chip with multiple processors; shared bus interface
Private vs Shared Cache
  • Private is closer to core; faster access, but needs to make sure data is consistent with other caches (invalidation & snooping)
  • Shared has more space for content; needs to watch out for multiple cores accessing the same cache
Two-Pass Assembly
  • Pass 1 – build table linking label with offsets from x, where main label is at x
  • Pass 2 – build table linking addresses (relative to x) with instructions
MIPS Virtual Memory
  • Bottom 0x7fffffff, stack, heap, data, 0x10000000, text, 0x400000, reserved
  • $sp points to the top of the stack; decrease to store more data, increase to "clear" data
  • $fp points to the start of the stack for a given subroutine
  • $gp points to first byte in .data
Subroutine Conventions
  • Register convention – pass params with $a0-$a3, return with $v0, $v1; fast but limited registers
  • ANSI C standard – use stacks ($sp); simulates local vars; slows down program
MIPS – Push & Pop
# Push
subi $sp, $sp, 8
sw $s0, ($sp)
sw $s1, 4($sp)
# Pop
lw $s0, ($sp)
lw $s1, 4($sp)
addi $sp, $sp, 8
MIPS Function Calls
jal func # jump to label and track address

 j $ra # pointer to function caller
I/O (Polling, Interrupt, DMA, Synchronous, Asynchronous)
  • Polling – keep checking status until ready; blocks CPU, small overhead
  • Interrupt – wait for peripheral callback before resuming that activity; requires special hardware; sleeps current program; CPU is free to do other stuff; bigger overhead
  • DMI/DMA – direct memory interfacing/addressing – private bus; direct interface to RAM
  • Synchronous – send/read byte by byte (polling)
  • Asynchronous – load register with start address, another with limit, does other stuff until interrupt is received
Amdahl's Law
  • Speedup in performance is proportional to new component & actual fraction of work it carries out
  • s = 1/[(1 – f) + f/k]  Where s is speedup, f is fraction of work by component, k is advertised speedup